EDPIDR0, External Debug Peripheral Identification Register 0

The EDPIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information, see 'About the Peripheral identification scheme'.

When FEAT_DoPD is implemented, EDPIDR0 is in the Core power domain. Otherwise, EDPIDR0 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

EDPIDR0 is a 32-bit register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								PART_0

Reserved, RES0.

Part number, least significant byte.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Component	Offset	Instance
Debug	0xFE0	EDPIDR0

This interface is accessible as follows:

When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
Otherwise, accesses to this register are RO.

19/09/2024 21:51; f38fb98db05c9431684175106ec86e1bac8166e3