Arm Instruction Set Architecture
A64 is the instruction set used in AArch64, supported by the Armv8-A, Armv8-R AArch64 and Armv9-A architectures.
Key features of A64 include:
Clean decode table based on 5-bit register specifiers. Instruction semantics broadly similar to A32 and T32. 31 general-purpose 64-bit registers accessible at all times. No modal banking of general purpose registers for improved performance and energy. Program counter and stack pointer are not general purpose registers. Dedicated zero register available for most instructions.
Official documentation
Documentation – Arm Developer ↗
Arm A-profile Architecture Registers ↗
Arm A-profile A64 Instruction Set Architecture ↗
Arm A-profile A32/T32 Instruction Set Architecture ↗
Local A64 instruction set (2024-06)
Unofficial HTML dump of the Arm A-profile A64 XML. Prefer the official manuals above for anything serious.
- Base instructions
- SIMD and FP instructions
- SVE instructions
- SME instructions
- Index by encoding
- Shared pseudocode
Local A-profile registers (2024-06)
Unofficial HTML dump of the Arm A-profile System Register XML.
- AArch64 registers
- AArch64 system instructions
- AArch32 registers
- AArch32 system instructions
- External registers (alphabetic)
- Functional index
- Encoding index
Newer XML releases can be copied alongside these versioned folders with make sync-arm when a local arm/ dump is present.