DIVPS — Divide Packed Single Precision Floating-Point Values
| Opcode/Instruction | Op / En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| NP 0F 5E /r DIVPS xmm1, xmm2/m128 | A | V/V | SSE | Divide packed single precision floating-point values in xmm1 by packed single precision floating-point values in xmm2/mem. |
| VEX.128.0F.WIG 5E /r VDIVPS xmm1, xmm2, xmm3/m128 | B | V/V | AVX | Divide packed single precision floating-point values in xmm2 by packed single precision floating-point values in xmm3/mem. |
| VEX.256.0F.WIG 5E /r VDIVPS ymm1, ymm2, ymm3/m256 | B | V/V | AVX | Divide packed single precision floating-point values in ymm2 by packed single precision floating-point values in ymm3/mem. |
| EVEX.128.0F.W0 5E /r VDIVPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst | C | V/V | AVX512VL AVX512F | Divide packed single precision floating-point values in xmm2 by packed single precision floating-point values in xmm3/m128/m32bcst and write results to xmm1 subject to writemask k1. |
| EVEX.256.0F.W0 5E /r VDIVPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst | C | V/V | AVX512VL AVX512F | Divide packed single precision floating-point values in ymm2 by packed single precision floating-point values in ymm3/m256/m32bcst and write results to ymm1 subject to writemask k1. |
| EVEX.512.0F.W0 5E /r VDIVPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst{er} | C | V/V | AVX512F | Divide packed single precision floating-point values in zmm2 by packed single precision floating-point values in zmm3/m512/m32bcst and write results to zmm1 subject to writemask k1. |
Instruction Operand Encoding ¶
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (r, w) | ModRM:r/m (r) | N/A | N/A |
| B | N/A | ModRM:reg (w) | VEX.vvvv (r) | ModRM:r/m (r) | N/A |
| C | Full | ModRM:reg (w) | EVEX.vvvv (r) | ModRM:r/m (r) | N/A |
Description ¶
Performs a SIMD divide of the four, eight or sixteen packed single precision floating-point values in the first source operand (the second operand) by the four, eight or sixteen packed single precision floating-point values in the second source operand (the third operand). Results are written to the destination operand (the first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.
Operation ¶
VDIVPS (EVEX Encoded Versions) ¶
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] := SRC1[i+31:i] / SRC2[31:0]
ELSE
DEST[i+31:i] := SRC1[i+31:i] / SRC2[i+31:i]
FI;
ELSE
IF *merging-masking* ; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE ; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VDIVPS (VEX.256 Encoded Version) ¶
DEST[31:0] := SRC1[31:0] / SRC2[31:0] DEST[63:32] := SRC1[63:32] / SRC2[63:32] DEST[95:64] := SRC1[95:64] / SRC2[95:64] DEST[127:96] := SRC1[127:96] / SRC2[127:96] DEST[159:128] := SRC1[159:128] / SRC2[159:128] DEST[191:160] := SRC1[191:160] / SRC2[191:160] DEST[223:192] := SRC1[223:192] / SRC2[223:192] DEST[255:224] := SRC1[255:224] / SRC2[255:224]. DEST[MAXVL-1:256] := 0;
VDIVPS (VEX.128 Encoded Version) ¶
DEST[31:0] := SRC1[31:0] / SRC2[31:0] DEST[63:32] := SRC1[63:32] / SRC2[63:32] DEST[95:64] := SRC1[95:64] / SRC2[95:64] DEST[127:96] := SRC1[127:96] / SRC2[127:96] DEST[MAXVL-1:128] := 0
DIVPS (128-bit Legacy SSE Version) ¶
DEST[31:0] := SRC1[31:0] / SRC2[31:0] DEST[63:32] := SRC1[63:32] / SRC2[63:32] DEST[95:64] := SRC1[95:64] / SRC2[95:64] DEST[127:96] := SRC1[127:96] / SRC2[127:96] DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent ¶
VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);
VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);
DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions ¶
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
Other Exceptions ¶
VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”